This invention relates generally to the design of integrated circuits and more particularly, relates to the automated placement of a clock distribution network during the design of an integrated circuit.
The term chip or integrated circuit as used herein is understood to be thousands to millions of transistors manufactured on a semiconductor substrate and wired together to perform a specific function. The wiring may be aluminum or copper or other conductive material. The number of transistors on a chip, the speed of each transistor, and the delay passing electricity through each transistor and each metal interconnect determine how fast the entire chip operates. The transistors may be configured into logic gates, RAM and/or ROM memory, I/O latches and circuits which input and output signals to and from the chip. Integrated circuits can be categorized into two broad classes: (1) custom circuits; and (2) application specific integrated circuits (ASICs). Custom integrated circuits are uniquely characterized and frequently require manual effort and much time to physically design the circuit. An example of a custom chip is a microprocessor circuit. Designing an ASIC, on the other hand, requires less time using existing technologies and circuits because the circuit is more straightforward. An example of an ASIC is a memory interface circuit.
During integrated circuit design, design engineers pay particular attention to the structure of the clock distribution network. The clock distribution network is the logical and physical structure which provides the pulse to strictly maintain the correct sequence of events throughout the integrated circuit. Such events include receiving and sending data through I/O circuits, on-chip processing and logical operation, and storage of data in memory. Clock signals are typically distributed from a single clock source to many destinations which may be located far apart within the computer. For several reasons, the clock signals do not arrive at all destinations the same time and the difference in time between the arrival of the clock signal at different destinations is called skew. As computers become faster and faster because their clock frequency increases, skew becomes a substantial percentage of the clock period and may actually limit the speed at which the computer can operate. In a physically larger computer system, moreover, the distance between destinations and the clock distribution circuits can vary dramatically, increasing clock skew.
A typical path for a clock signal includes many electronic components, such as gates, integrated circuit (IC) interconnect metals, and wires. Each of these provides an opportunity for introducing undesired clock skew. The amount of time it takes a signal to travel along a wire is called its electrical length, and it depends upon the physical length, the capacitance, and the resistance of the wire path. All else being equal, a signal takes more time to travel a long path than a short one. If the electrical lengths of all the clock signal paths are not equal, skew is introduced.
The clock distribution network often further includes several levels of fanout gates and amplifiers or drivers. Skew results if there are unequal numbers of gates in separate signal paths or if there are variations in how long it takes a signal to pass through different gates. How long it takes a signal to pass through a gate depends upon several factors including the propagation delay characteristics of the particular type of gate, the number of loads the gate is driving, and the temperature of the gate. Any variation of these parameters between two signal paths will cause skew in the signals. Even if these factors are identical, there may be variations between individual gates of the same type.
Crosstalk from adjacent signals can be another cause of clock skew. For example, if during a transition from one logic state to another, a signal""s voltage level is altered by crosstalk, then the point in time when the signal is determined to have switched will be altered, thus introducing skew. Another source of skew is when the logic level is determined by reference to a power supply voltage. For example, if the logic levels are defined as voltages relative to ground, any noise on a logic gate""s ground reference will affect the time at which the gate determines an input signal to have switched.
There are reasons to minimize and, if possible, to eliminate skew. First, skew limits the speed at which a computer system can operate. Computer tasks are often performed serially with data passed from one stage of the computer to another on subsequent clock cycles. The time period of the clock must be sufficient for a stage to process the data and propagate it to the next stage. In addition, the clock period must allow for any skew between the clock signals at the various stages. For example, if one stage is clocked late because of skew but the next stage is clocked on time, the data from the first stage may not yet have arrived when the second stage is clocked. The clock period thus must be stretched to accommodate not only the time needed for the first stage to process and propagate the data, but also for skew between the clock signals present at the two stages. On the other hand, clock skew may prevent a system from slowing down when the clock frequency is decreased. A clocked electronic system, moreover, may not function at any frequency because of early mode timing faults caused by clock skew.
Computers are typically designed modularly with circuitry placed on various removable circuit boards or modules. Without consideration of the effects of clock skew in the system, the ability of a board or module to be interchanged from one machine to another is severely constrained or even prohibited. The amount of clock skew on a particular module may be different from that on other modules because the time it takes a signal to propagate through a particular type of logic gate varies from gate to gate and each module may have different types and numbers of gates. A system designed to accommodate skew present on one module may not work with other modules. The result is that some modules may not function in all machines because of clock skew.
There are several techniques to reduce clock skew. The design engineer can attempt to equalize the wire between the clock source and all destinations by distributing the clock signals radially from a clock distribution point physically located near the center of the machine. The designer can also equalize the number of gates and types of gates in all clock signal paths. Clock skew can also be reduced by equalizing the load driven by gates and various signal paths. Because these techniques affect the fundamental layout of the circuits, they can only be performed during the physical layout of the system.
There are also techniques to introduce delay into the clock distribution network that can be performed either or both during the design and during the manufacture or installation of the system. The critical parameter is the difference in delay between the various signal paths, not the actual amount of delay in any given path. Thus, a specific amount of delay is introduced in the faster signal paths to match the electrical length of the slowest signal paths and thus compensate for skew. Delay line tuning involves connecting a clock signal path through a delay line to provide multiple outputs, each corresponding to a different delay amount. The output corresponding to the needed delay is selected at the time of installation by reference to other clock signal paths.
The effectiveness and practicality of these methods varies. Equalizing trace lengths, number of gates, and loading must be done during the initial design phase and, as such, cannot account for design changes or component variations. Equalizing the number of gates in the path and the gate loading may not be possible in all circumstances because of other design constraints of the circuit. A previously equalized circuit may require the addition of new circuitry not conceived of during the initial design phase and the equalized paths may no longer be equalized after the addition of new circuitry. Delay line tuning, however, is adjustable and can skew compensate a circuit even after the addition of new circuitry.
The design of the clock distribution network, however, is only part of the physical design process. The clocking logic must be placed and routed along with the rest of the logic of the entire integrated circuit. The term xe2x80x9cplacedxe2x80x9d refers to the assignment of a specific location of the individual components on the integrated circuit. Automated placement is performed by software programs capable of manipulating and moving very large number of circuits, gates, latches, etc, during the design to be placed on the semiconductor substrate of an integrated circuit. Automated routing refers to the interconnection of the circuits by a software program during design.
The physical design process thus must meet not only the skew requirements of the clock distribution network but must further meet the demands of the entire automated placement and routing of the integrated circuit. Historically, the clock requirements have interfered with the physical design process because some logic circuits need be delayed, others not so much or not at all thus making the placement and routing process for the entire integrated circuit including the clock distribution network a difficult and time-consuming aspect of its design.
It is thus an object of the present invention to provide an automated procedure to include clock distribution in the design of an integrated circuit.
This object and other objects and advantages that will become apparent are realized by a method of automated placement of circuit elements in the design of an integrated circuit, comprising the steps of defining a plurality of bounding boxes, each bounding box having a root driver and within the bounding box, connecting a first circuit element of at least one user-defined placement group to each root driver maintaining substantially the same capacitance target within all of said bounding boxes. The root driver may be a driver circuit of a clock circuit in a clock distribution network. Further, the clock distribution network may be a second level clock distribution network of a computer system memory interface. In an embodiment, the user-defined group may comprise a plurality of circuit elements comprising a gate connected to the root driver as a first circuit element, a clock delay to receive the output of the gate, and a clock splitter connected to receive the output of the clock delay. The clock delay may further be a programmable clock delay in which the first stage of the programmable delay is contained within the bounding box. The clock delay, moreover, may have more than one stage and may have multiple programmable stages.
In a preferred embodiment of the invention, the invention may be considered a method of automated design of a clock distribution network having minimal clock skew throughout an integrated circuit, comprising the steps of defining a plurality of bounding boxes having tightly-coupled logic, each of the bounding boxes having a clock root driver connected to an input source of a clock signal; connecting at least a user-defined placement clock delay group within each bounding box to each root driver maintaining substantially the same wire capacitance target and input pin load balance for each of the user-defined placement clock delay groups having a same clock delay within all of the bounding boxes, in which the user-defined placement clock delay group comprises having a gate connected to the root driver, a first stage of a programmable delay electrically connected to the gate, and a clock splitter connected to the output of the programmable delay.
In another embodiment of the invention of designing an integrated circuit, the method may comprise inputting a design specification of the integrated circuit having a clock source into an automated design program; determining the number of clock circuits required for the integrated circuit; dividing the design of the integrated circuit into as many areas as the number of clock circuits and preplacing a clock root driver connected to the clock source in a central area of each of the areas. The method further comprises placing tightly-coupled logic together in a vicinity surrounding each of the clock root drivers and in each of the vicinities, placing user-defined groups of the tightly-coupled logic to be electrically connected to the clock root driver in each of the vicinities; determining capacitance targets for a critical circuit element of each of the user-defined groups such that the critical circuit element of one of the vicinities corresponding to the same critical circuit element of any other vicinity is within the same capacitance target of the clock root driver; and then recording the coordinates of each clock root driver and each critical circuit element for each vicinity.
The invention may further be realized in a computer readable medium having an executable program operative to control a computer for designing a clock signal distribution network on an integrated circuit, the program comprising: evaluating a specification for an integrated circuit with respect to the clock signal distribution network and determining the level and number of clock distribution circuits having tightly-coupled logic required for the integrated circuit; arranging the clock distribution circuits from an input source of the clock signal so that the clock distribution circuits are distributed on the integrated circuits; placing a root driver connected to the input source in each of the clock distribution circuits; and placing a number of user-defined placement clock delay circuit groups to be electrically connected within a capacitance target to the root driver such that the capacitance target for one of the user-defined placement clock delay circuit groups in one of the clock distribution circuits is substantially the same as the capacitance target of the same user-defined placement clock delay circuit group of another of the clock distribution circuits.
The invention is also an apparatus to design a signal distribution network in an integrated circuit, comprising a means to input a design specification of the integrated circuit wherein the design specification has an input source of an electronic signal to be distributed throughout the integrated circuit; a means to route the signal from the input source to a plurality of areas in which tightly-coupled logic circuits are to be placed, a means to place a signal root driver in each of the areas, a means to determine a capacitance target for a number of user-defined placement groups to be connected to each signal root driver such that the capacitance target minimizes skew of the signal distributed throughout the integrated circuit, a means to place the user-defined placement groups in each of the areas in accordance with the capacitance targets, and a means to record positions of the signal root driver and the user-defined placement groups.